An electrostatic discharge (ESD) pulse is a sudden and unexpected voltage and/or current discharge that transfers energy to an electronic device from an outside body, such as from a human body for example. ESD pulses can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure.
To protect electronic devices from ESD pulses, engineers have developed ESD protection devices. FIG. 1 shows an example of an integrated circuit 100 that includes an ESD-susceptible circuit 102 that can be electrically connected to an exterior circuit assembly (not shown) via external IC pins 104A, 104B. A conventional ESD protection device 106 is electrically connected between circuit 102 and external pins 104A, 104B to mitigate damage due to an ESD pulse 108, if present. If an ESD pulse 108 occurs, a trigger element 110 detects ESD pulse 108 and provides a trigger signal 112 to a silicon controlled rectifier (SCR) 114. In response to this trigger signal 112, SCR 114 quickly shunts energy of ESD pulse 108 away from circuit 102 (e.g., as shown by arrow WESD), thereby preventing damage to circuit 102.
FIG. 2A shows one depiction of an SCR device 200, which is often implemented as a pair of tightly coupled bipolar junction transistors (BJTs) 202A, 202B, such as shown in FIG. 2B. In such an SCR device 200, when the gate-to-cathode voltage exceeds a certain threshold, SCR 200 turns “on”. Thus, when ESD event 108 is impingement and trigger element 110 asserts its trigger signal 112 in FIG. 1, SCR 114 turns “on” and diverts power of ESD pulse 108 away from circuit 102. SCR 114 will remain “on” even after gate current is removed so long as current/voltage through SCR 114 remains above a holding current/voltage. Once current/voltage falls below the holding current/voltage for an appropriate period of time (e.g., once ESD event 108 has passed), SCR 114 will switch “off” and normal blocking operation will resume.
Although this methodology is generally effective in the ESD context, until now it has been burdensome to set accurate trigger and holding voltages/currents for traditional SCR devices across technologies. For example, one manufacturing flow may be designed for circuit 102 to be powered by a 5 V supply from external IC pin, while another manufacturing flow may be designed for circuit 102 (or some variation thereof) to be powered by a 1.2V supply. If rigorous design and testing is not carried out, SCR 114 could inadvertently be triggered (e.g., if trigger voltage is set too low) or could divert power for too long (e.g., if holding current is set too low); leading to problems in operation. As will be appreciated in greater detail below, the present disclosure relates to improved SCR devices which allow independent and robust running of trigger and holding voltages by using simple layout parameters. These tunable Fin-SCRs are beneficial in ESD protection devices, such as shown in FIG. 1 for example, as well as other circuits.